Throughout the specification, including in the claims, the expression “auxiliary data” is used in a broad sense to denote digital audio data or any other data that is neither video data nor timing information for video data (e.g., a video clock). For example, timing information for audio data (e.g., a clock for recovering transmitted audio data) falls within the scope of “auxiliary data.” Other examples of “auxiliary data” transmitted in accordance with the invention include computer keyboard signals, still image data (generated by a camera, for example), text data, control signals for a power supply, picture in picture data, monitor control information (audio volume, brightness, power state), control signals for indicator lights on a monitor or keyboard, non-audio or video control information, etc.
Throughout the specification, including in the claims, the expression “audio data” denotes not only digital audio data samples but also data included (with digital audio data samples) in audio data packets. For example, a 32-bit packet (“sub-frame”) of SPDIF audio data includes a 20-bit sample of audio data and twelve additional bits (including a 4-bit “B,” “M,” or “W” preamble), and all 32 such bits are “audio data” bits as defined herein.
The term “stream” of data, as used herein, denotes that all the data are of the same type and is transmitted with the same clock frequency. The term “channel,” as used herein, refers to that portion of a serial link that is employed to transmit data (e.g., a particular conductor or conductor pair between a transmitter and receiver over which the data are transmitted, and specific circuitry within the transmitter and/or receiver used for transmitting and/or recovery of the data) and to the technique employed to transmit the data over the link. A channel can be employed to transmit one stream of data, or more than one stream of data.
The term “transmitter” is used herein in a broad sense to denote any device capable of encoding data and transmitting the encoded data over a serial link (and optionally also performing additional functions, which can include encrypting the data to be transmitted and other operations related to encoding, transmission, or encryption of the data). The term “receiver” is used herein in a broad sense to denote any device capable of receiving and decoding data that has been transmitted over a serial link (and optionally also performing additional functions, which can include decrypting the received data and other operations related to decoding, reception, or decryption of the received data). For example, the term transmitter can denote a transceiver that performs the functions of a receiver as well as the functions of a transmitter. In a more specific example, the term transmitter (with reference to a device that transmits non-audio auxiliary data over a serial link) can denote a transceiver that is configured to receive video data and audio data over the link and to transmit the non-audio auxiliary data over the link.
Various serial links for transmitting data and clock signals are well known.
One conventional serial link, used primarily for high-speed transmission of video data from a host processor (e.g., a personal computer) to a monitor, is known as a transition minimized differential signaling interface (“TMDS” link). The characteristics of a TMDS link include the following:
1. video data are encoded and then transmitted as encoded words (each 8-bit word of digital video data is converted to an encoded 10-bit word before transmission);                a. the encoding determines a set of “in-band” words and a set of “out-of-band” words (the encoder can generate only “in-band” words in response to video data, although it can generate “out-of-band” words in response to control or sync signals. Each in-band word is an encoded word resulting from encoding of one input video data word. All words transmitted over the link that are not in-band words are “out-of-band” words);        b. the encoding of video data is performed such that the in-band words are transition minimized (a sequence of in-band words has a reduced or minimized number of transitions);        c. the encoding of video data is performed such that the in-band words are DC balanced (the encoding prevents each transmitted voltage waveform that is employed to transmit a sequence of in-band words from deviating by more than a predetermined threshold value from a reference potential. Specifically, the tenth bit of each “in-band” word indicates whether eight of the other nine bits thereof have been inverted during the encoding process to correct for an imbalance between running counts of ones and zeroes in the stream of previously encoded data bits);        
2. the encoded video data and a video clock signal are transmitted as differential signals (the video clock and encoded video data are transmitted as differential signals over conductor pairs);
3. three conductor pairs are employed to transmit the encoded video, and a fourth conductor pair is employed to transmit the video clock signal; and
4. signal transmission occurs in one direction, from a transmitter (typically associated with a desktop or portable computer, or other host) to a receiver (typically an element of a monitor or other display device).
Another serial link is the “High Definition Multimedia Interface” interface (“HDMI” link) developed Silicon Image, Inc., Matsushita Electric, Royal Philips Electronics, Sony Corporation, Thomson Multimedia, Toshiba Corporation, and Hitachi.
Another serial link is the “Digital Visual Interface” interface (“DVI” link) adopted by the Digital Display Working Group. It will be described with reference to FIG. 1. A DVI link can be implemented to include two TMDS links (which share a common conductor pair for transmitting a video clock signal) or one TMDS link, as well as additional control lines between the transmitter and receiver. The DVI link of FIG. 1 includes transmitter 1, receiver 3, and a cable (comprising connectors 120 and 121 and conductor set 122) between the transmitter and receiver. Conductor set 122 comprises four conductor pairs (Channel 0, Channel 1, and Channel 2 for video data, and Channel C for a video clock signal), Display Data Channel (“DDC”) lines for bidirectional communication between the transmitter and a monitor associated with the receiver in accordance with the conventional Display Data Channel standard (the Video Electronics Standard Association's “Display Data Channel Standard,” Version 2, Rev. 0, dated Apr. 9, 1996), a Hot Plug Detect (HPD) line (on which the monitor transmits a signal that enables a processor associated with the transmitter to identify the monitor's presence), Analog lines (for transmitting analog video to the receiver), and Power lines (for providing DC power to the receiver and a monitor associated with the receiver). The Display Data Channel standard specifies a protocol for bidirectional communication between a transmitter and a monitor associated with a receiver, including transmission by the monitor of an Extended Display Identification (“EDID”) message that specifies various characteristics of the monitor, and transmission by the transmitter of control signals for the monitor. Transmitter 1 includes three identical encoder/serializer units (units 2, 4, and 6) and additional circuitry (not shown). Receiver 3 includes three identical recovery/decoder units (units 8, 10, and 12) and inter-channel alignment circuitry 14 connected as shown, and additional circuitry (not shown).
As shown in FIG. 1, circuit 2 encodes the data to be transmitted over Channel 0, and serializes the encoded bits. Similarly, circuit 4 encodes the data to be transmitted over Channel 1 (and serializes the encoded bits), and circuit 6 encodes the data to be transmitted over Channel 2 (and serializes the encoded bits). Each of circuits 2, 4, and 6 responds to a control signal (an active high binary control signal referred to as a “data enable” or “DE” signal) by selectively encoding either digital video words (in response to DE having a high value) or a control or synchronization signal pair (in response to DE having a low value). Each of encoders 2, 4, and 6 receives a different pair of control or synchronization signals: encoder 2 receives horizontal and vertical synchronization signals (HSYNC and VSYNC); encoder 4 receives control bits CTL0 and CTL1; and encoder 6 receives control bits CTL2 and CTL3. Thus, each of encoders 2, 4, and 6 generates in-band words indicative of video data (in response to DE having a high value), encoder 2 generates out-of-band words indicative of the values of HSYNC and VSYNC (in response to DE having a low value), encoder 4 generates out-of-band words indicative of the values of CTL0 and CTL1 (in response to DE having a low value), and encoder 6 generates out-of-band words indicative of the values of CTL2 and CTL3 (in response to DE having a low value). In response to DE having a low value, each of encoders 4 and 6 generates one of four specific out-of-band words indicative of the values 00, 01, 10, or 11, respectively, of control bits CTL0 and CTL1 (or CTL2 and CTL3).
It has been proposed to encrypt video data transmitted over a serial link. For example, it has been proposed to use a cryptographic protocol known as “High-bandwidth Digital Content Protection” (“HDCP”) to encrypt digital video to be transmitted over a DVI link and to decrypt the data at the DVI receiver. A DVI transmitter implementing HDCP outputs a 24-bit bus, known as cout[23:0], during the video active period (i.e. when DE is high). This 24-bit cout data is “Exclusive Ored” (in logic circuitry in the transmitter) with the 24-bit RGB video data input to the transmitter in order to encrypt the video data. The encrypted data is then encoded (according to the TMDS standard) for transmission. The same cout data is also generated in the receiver. After the encoded and encrypted data received at the receiver undergoes TMDS decoding, the cout data is processed together with the decoded video in logic circuitry in order to decrypt the decoded data and recover the original input video data.
Typically, the primary data transmitted by a TMDS link are video data. The video data are not continuous, and instead have blanking intervals. These blanking intervals provide an opportunity for auxiliary data to be transported, and they represent unused bandwidth. However, many serial links do not transmit data having blanking intervals, and thus do not encode input data (for transmission) in response to a data enable signal. For example, audio serial links would typically transmit continuous data.
In some systems of the type described in above-referenced U.S. patent application Ser. No. 10/171,860, a serial link is coupled between a transmitter and a receiver, and the transmitter sends video data, packetized audio data, and a video clock over the link to the receiver. Circuitry in the transmitter uses the video clock to generate cycle time stamps (for use in regenerating an audio clock for the audio data) and the transmitter transmits “time stamp” data (data indicative of the cycle time stamps) to the receiver over the link. The receiver is configured to regenerate an audio clock for the audio data in response to the time stamp data and video clock. Each cycle time stamp (“CTS”) is the number of video clock cycles in a defined (predetermined) audio period. The audio period is typicallyN/(128*Fs)where Fs is the audio sample frequency and N is a user-specified number, in which case each CTS value is:CTS=(N*Fp)/(128*Fs)where Fp is the video clock frequency. A video clock is sometimes referred to herein as a “pixel clock,” and the frequency of a video clock (e.g., “Fp”) is sometimes referred to herein as a “pixel clock frequency.”
We will use the expression “embedded-clock audio stream” (or “embedded-clock audio data”) to denote audio data stream (e.g., an SPDIF audio stream) in which an audio clock is embedded such that the audio clock is not readily available, and the expression “embedded-clock auxiliary data stream” (or “embedded-clock audio data”) to denote a stream of auxiliary data in which an auxiliary data clock is embedded such that the auxiliary data clock is not readily available. In the case that an embedded-clock audio stream (e.g., an SPDIF audio stream) is input to a transmitter, and no audio clock for the input audio is separately provided to the transmitter (e.g., from an external device), circuitry in the transmitter is needed to extract an audio clock from the input audio, for use in generating the CTS values. If the extracted audio clock has frequency Z*Fs, the transmitter could generate a sequence of CTS values by repeatedly counting the number of video clock cycles in N cycles of the audio clock. If the frequency of the extracted audio clock were a multiple of Z*Fs, such as 2Z*Fs or 3Z*Fs, a divider circuit could be employed to generate a desired Z*Fs clock from the extracted clock.
A phase-locked loop (PLL) could be employed to extract an audio clock from an embedded-clock audio stream. However, it is difficult and costly to implement a suitable PLL in a typical transmitter for this purpose. Including such a PLL in the transmitter would add significantly to the cost of designing and manufacturing the transmitter. Inclusion of a PLL in an integrated circuit (configured to generate a sequence of CTS values from a video clock and an SPDIF or other embedded-clock audio stream) would consume costly integrated circuit real estate and development resources, and would add integration complexities to the integrated circuit.